ALL; entity johnson_counter is port (     DAT_O : out unsigned(3 downto 0);     RST_I : in std_logic;     CLK_I : in std_logic     ); finis johnson_counter; computer architecture behavioural of johnson_counter is mark interim : unsigned(3 downto 0):=(others => 0); begin DAT_O <= temp; sue(CLK_I) begin   if( rising_edge(CLK_I) ) then     if (RST_I = 1) then       temp <= (others => 0);     else       temp(1) <= temp(0);       temp(2) <= temp(1);       temp(3) <= temp(2);       temp(0) <= not temp(3);     end if;   end if; end process;   end Behavioral; The testbench code used for testing the visualize is given at a lower place: LIBRARY ieee; lend oneself ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb2 IS death tb2; ARCHITECTURE way OF tb2 IS   --Inputs   signal RST_I : std_logic := 0;   signal CLK_I : std_logic := 0;   --Outputs   signal DAT_O : unsigned(3 downto 0);   -- clock period definitions   constant quantity CLK_I_period : time := 1 ns; BEGIN   -- instantiate the unit Under interrogation (UUT)   uut: entity work.johnson_counter PORT MAP (      DAT_O => DAT_O,      RST_I => RST_I,      CLK_I => CLK_I     );   -- Clock...If you pauperism to get a blanket(a) essay, order it on our website: Orderessay
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